(a) Field of the Invention
The present invention relates to a thin film transistor (TFT) array substrate for a liquid crystal display, and a method for fabricating the same.
(b) Description of the Related Art
A liquid crystal display is one of flat panel display devices that has been currently used in a most extensive manner. The liquid crystal display has two substrates, and a liquid crystal layer sandwiched between the substrates. One of the substrates is provided with thin film transistors (TFTs), and pixel electrodes. The TFT array substrate is fabricated through forming thin films on the substrate, and repeatedly performing photolithography on the thin films.
The number of masks employed in the photolithography process that represents the number of processing steps becomes to be a critical factor to reduce the production cost. In order to lower the production cost, it is required that the number of masks for the photolithography process should be reduced.
It is an object of the present invention to provide a method for fabricating a TFT array substrate for a liquid crystal display, which involves simplified processing steps.
This and other objects may be achieved by a method for fabricating a TFT array substrate for a liquid crystal display where a data line assembly, pixel electrodes and a semiconductor pattern are formed at only one photolithography process.
The method for fabricating a TFT array substrate for a liquid crystal display includes the step of forming a gate line assembly and a common electrode line assembly on a first substrate. The gate line assembly includes a plurality of gate lines and gate pads, and the common electrode line assembly includes common signal lines and common electrodes. Thereafter, a gate insulating layer is formed on the first substrate, and a semiconductor pattern and an ohmic contact pattern are formed on the gate insulating layer. A data line assembly and pixel electrodes are then formed on the first substrate. The data line assembly includes a plurality of data lines, data pads, and source and drain electrodes. The pixel electrodes are connected to the drain electrodes while proceeding parallel to the common electrodes. A passivation layer is formed on the substrate. The passivation layer and the gate insulating layer are etched such that the gate pads and the data pads are exposed to the outside. At this time, the etching is performed after an assembly process where a second substrate is arranged to face the first substrate, and the passivation layer and the gate insulating layer are exposed externally to the second substrate.
Alternatively, the step of exposing the gate and the data pads may be performed after the step of injecting liquid crystal molecules in-between the first and the second substrates facing each other, and sealing the gap between the first and second substrates. Furthermore, a sealant may be partially coated onto the gate and the data pads.
The steps of forming the data line assembly, the pixel electrodes, the ohmic contact pattern and the semiconductor pattern are made through photolithography based on one photoresist pattern having different thickness. The photoresist pattern has a first portion placed between the source and the drain electrodes with a predetermined thickness, a second portion for forming the data line assembly and the pixel electrodes that is thicker than the first portion, and a third portion that is thinner than the first portion.
The photoresist pattern is formed using a mask with a thin film with a light transmission of 20 to 50% corresponding to the first portion of the photoresist pattern, and a thin film with a light transmission of 3% or less corresponding to the second portion of the photoresist pattern.
Alternatively, the photoresist pattern may be made using a mask with a minute pattern corresponding to the area between the source and the drain electrodes while bearing an opening width smaller than the resolution of a light exposing device. The minute pattern may be either a slit pattern or a mosaic pattern with an opening width of 2 xcexcm or less.
Furthermore, supplemental data lines are formed at the step of forming the gate line assembly, and first contact holes exposing the upplemental data lines are formed at the step of forming the gate insulating layer. The steps of forming the ohmic contact pattern, the semiconductor pattern and the first contact holes are made through a photolithography based on one photoresist pattern having different in thickness. The photoresist pattern has a first portion corresponding to the ohmic contact pattern and the semiconductor pattern with a predetermined thickness, a second portion that is thicker than the first portion, and a third portion corresponding to the first contact holes that is thinner than the first portion.
The pixel electrodes are formed in a linear shape while proceeding parallel to the common electrodes.
The method further includes the step of forming one or more light interception patterns to be placed at the same plane as the gate lines with the same material such that each light interception pattern is separated from the gate line and positioned close to the neighboring subsidiary data line while proceeding parallel thereto. The pixel electrodes are partially overlapped with the light interception patterns. Alternatively, the pixel electrodes may be spaced apart from the light interception patterns by 2 xcexcm or less.
The method further includes the steps of forming a gate short circuit line such that the gate short circuit line is connected to the gate pads, forming a second contact hole at the gate insulating layer such that the second contact hole exposes the gate short circuit line, and forming a data short circuit line such that the data short circuit line is connected to the data pads, the data short circuit line being connected to the gate short circuit line through the second contact hole.
In the meantime, the liquid crystal display includes a first substrate, and a gate line assembly and a common electrode line assembly formed on the first substrate. The gate line assembly includes a plurality of gate lines proceeding in the horizontal direction and gate pads connected to the gate lines, and the common electrode line assembly includes common signal lines proceeding parallel to the gate lines and common electrodes connected to the common signal lines while proceeding in the vertical direction. A gate insulating layer covers the gate line assembly and the common electrode line assembly, and a semiconductor pattern is formed on the gate insulating layer. An ohmic contact pattern is formed on the semiconductor pattern. A data line assembly and pixel electrodes are further formed at the first substrate. The data line assembly includes a plurality of data lines formed on the gate insulating layer and the ohmic contact pattern while crossing over the gate lines to form pixel regions, data pads connected to the data lines, source electrodes being parts of or branched from the data lines, and drain electrodes separated from the source electrodes. The pixel electrodes are connected to the drain electrodes at the pixel regions while proceeding parallel to the common electrodes. A passivation layer covers the data line assembly and the pixel electrodes. A second substrate faces the first substrate. The gate insulating layer and the passivation layer exposed externally to the second substrate and the data pads are removed.
The ohmic contact pattern has the same shape as the data line assembly and the pixel electrodes, and the semiconductor pattern has the same shape as the data line assembly and the pixel electrodes except for the area between the source and the drain electrodes.
Furthermore, subsidiary data lines are formed at the same plane as the gate line assembly with the same material, and first contact holes are formed on the gate insulating layer while exposing the subsidiary data lines.
Each pixel electrode is formed with two or more linear electrode portions, and each linear electrode portion is positioned close to the neighboring data line. Both ends of the linear electrode portions are connected to each other such that the pixel electrode bears a ring shape.
Furthermore, one or more light interception patterns are separated from the gate lines, and positioned close to the subsidiary data lines while proceeding parallel to the subsidiary data lines. The pixel electrodes are partially overlapped with the light interception patterns. Alternatively, the pixel electrodes are spaced apart from the light interception patterns by 2 xcexcm or less.
On the other hand, in another method of fabricating a TFT array substrate for a liquid crystal display according to the present invention, the shadow frame is used to prevent the semiconductor layer, or the gate insulating layer from being deposited on the gate pad portion.
The method of fabricating a thin film transistor array substrate for a liquid crystal display includes the step of forming a gate line assembly and a common electrode line assembly on a substrate including a display areas and a peripheral areas. The gate line assembly comprises a plurality of gate lines and gate electrode of the display areas, and gate pads of the peripheral areas, and the common electrode line assembly comprises common signal lines and common electrodes of the display areas. Next, a gate insulating layer covering the gate line assembly exposing the portions of the gate pads is formed, and the a semiconductor pattern and an ohmic contact pattern are formed on the gate insulating layer. A data line assembly and pixel electrodes are then formed on the substrate. The data line assembly includes a plurality of data lines, and source and drain electrodes of the display areas, and data pads of the peripheral areas. The pixel electrodes are connected to the drain electrodes while proceeding parallel to the common electrodes. Here, when forming a gate insulating layer, the shadow frame having a first blocking deposition areas is used to prevent the gate insulating layer from being deposited on the gate pad portion having the gate pads of the peripheral areas.
The shadow frame may have a second blocking deposition areas to prevent the gate insulating layer, the semiconductor pattern, or the ohmic contact pattern from being deposited on the data pad portion having the data pads of the peripheral areas.
The data line assembly, the pixel electrodes, the ohmic contact pattern and the semiconductor pattern may be made through photolithography based on one photoresist pattern having a different thickness. It is preferable that the photoresist pattern has a first portion placed between the source and the drain electrodes with a predetermined thickness, a second portion for forming the data line assembly and the pixel electrodes that is thicker than the first portion, and a third portion that is thinner than the first portion.
The data line assembly, the ohmic contact pattern and the semiconductor pattern may be made through a photolithography process using one mask. First, the gate insulating layer, a semiconductor layer, an ohmic contact layer, and a conductor layer are deposited, and a photoresist layer is coated on the conductor layer. Next, the photoresist layer is exposed to light through the mask to form a photoresist pattern such that the second portion lies on the data line assembly by developing the photoresist layer. The data line assembly, the ohmic contact layer pattern, and the semiconductor pattern respectively made of the conductor layer, the ohmic contact layer and the semiconductor layer are formed by removing a portion of the conductor layer under the third portion, the semiconductor layer and the ohmic contact layer thereunder, the first portion, the conductor layer and the ohmic contact layer under the first portion, and a partial thickness of the second portion, and the photoresist pattern is removed. In detail, the portion of the conductor layer under the third portion is removed by dry or wet etching to expose the ohmic contact layer, and the ohmic contact layer under the third portion, the semiconductor layer thereunder and the first portion are dry-etched to obtain a complete semiconductor pattern along with exposing the gate insulating layer under the third portion and the conductor layer under the first portion. The conductor layer under the first portion and the ohmic contact layer thereunder are removed to obtain a complete data wire and complete ohmic contact layer pattern.
The shadow frame may be used to prevent the semiconductor layer, the ohmic contact layer, or the conductor layer from being deposited on the gate pad portion of the peripheral areas when depositing the semiconductor layer, the ohmic contact layer, and the conductor layer, and the photoresist pattern may have a fourth portion placed on the gate pad portions, and having the thickness of the first, the second, or the third portion.
A mask used for forming the photoresist pattern has a first, a second, and a third part. It is preferable that the transmittance of the third part is higher than the first and the second parts, the transmittance of the first part is higher than the second part, the photoresist pattern is made of positive photoresist, and the mask is aligned such that the first, the second, and the third parts respectively face the first, the second, and the third portions of the photoresist pattern in an exposing step.
It is preferable that the first part of the mask includes a partially transparent layer, or a plurality of slit patterns smaller than the resolution of the exposure device used in the exposing step, and the first portion is formed by reflow.